Circuit design verification can require significant time and costly equipment, including both software and hardware. Currently, a behavioral description and test bench in hardware description language (HDL) are created for a design of a semiconductor device. Even if a behavioral description is not created, the design is coded in register transfer level (RTL) and simulated using a testbench. When the design is implemented in a target architecture, lengthy simulations using timing and functional models of the target architecture are run. As designs and technology are becoming more complex, the time required to run these simulations is becoming increasingly long. Although hardware accelerators and hardware emulators are helpful in verifying the design of a semiconductor device, these systems are typically quite expensive. In particular, licenses for software simulators and accompanying hardware peripherals can be prohibitively expensive.
Some of the high cost of these systems comes from the complexity of mapping designs onto the target architecture, especially for emulation systems. Although hardware accelerators are cheaper than emulators because they carry out simulation loading in vendor specific implementation models including timing information, their functionality is limited. That is, the format of the input data is limited to a format specific to the vendor.
Similarly, hardware prototype systems also have a number of drawbacks. Hardware prototype systems are usually in the form of logic analysis tools, from which it is possible to generate, apply and sample stimuli with any semiconductor system having digital inputs and outputs via test probes. However, these systems are not well suited for functional verification.
Accordingly, there is a need for an improved system and method for verifying a semiconductor design.